ÀÌ ±ÛÀº 2000³â Âë¿¡ Á¤¸®ÇÑ °ÍÀ¸·Î »õ·Î¿î ASICÀÇ ÇÕ¼º¿¡ ÁîÀ½ÇÏ¿© Àü¿¡ ´ë°­ ¾Ë°í ÀÖ´ø °ÍÀ» ´Ù½Ã remindÇÏ°í »õ·Î Áß¿äÇÑ ºÎºÐÀ» Á¤¸®Çϱâ À§ÇØ Kluwer Academic Publishers¿¡¼­ ³ª¿Â Logic Synthesis Using Synopsys, 2nd edition, by Pran Kurup & Taher Abbasi ¶ó´Â Ã¥À» Àдٰ¡ µ¹¹ßÀûÀ¸·Î Á¤¸®ÇÑ ±ÛÀÔ´Ï´Ù. ÇÕ¼º¿¡ ÀÖ¾î ±âº»ÀûÀÎ ±â¼úÀ», ¶Ç´Â °¡´ÉÇϸé Àü¹®ÀûÀÎ ±â¼úÀ» Å͵æÇÏ°í ½ÍÀ¸½Å ºÐÀ̶ó¸é Çѹø ÀÐ¾î º¸½Ã¸é µµ¿òÀÌ µÉ °ÍÀÔ´Ï´Ù. ¹°·Ð Á÷Á¢ ÀÏÀ» ÅëÇØ ¾î·Á¿î °æ¿ì¿Í ¾¾¸§À» ÇØ º¸°í dc_shellÀÇ ¸Å´º¾óÀ» ¸¹ÀÌ ÀÐ°í ½ÃµµÇØ º¸¾Æ¾ß ¿ÏÀüÈ÷ Å͵æÇÏ°ÚÁö¿ä?
(* ÀúÀÇ ÁÖÁ¾¸ñÀº ÁÖ·Î ASIC°³¹ß¿¡ ÀÖ¾î coding ¹× simulationÀ» ÅëÇÑ verificationÀ̶ó°í ÇÒ ¼ö ÀÖ½À´Ï´Ù ÇÕ¼ºÀ» ¸øÇß´ø °ÍÀº ¾Æ´Ï¾úÁö¸¸ ¸î ³â µ¿¾È ¿¬±¸¼Ò¿¡¼­ °³¹ßÇÑ ASIC¿¡¼­´Â ÇÕ¼ºÀº ÁÖ·Î ¿ÜºÎÀÇ ¿ë¿ªÈ¸»ç¿¡¼­ ÇÏ¿´±â ¶§¹®¿¡ codingÀ̳ª verification ±â¼ú¿¡ °É¸Â´Â ÇÕ¼º±â¼úÀ» Å͵æÇÒ ±âȸ°¡ ¾ø¾ú´ø °Í °°½À´Ï´Ù(ÇÕ¼ºÀÛ¾÷À» ÇÒ ¶§´Â ÁÖ·Î ¿·¿¡¼­ º¸´Â ÀÔÀåÀ̾úÁÒ). ±×·¯´Ù°¡ 2004³â¿¡ EPMC ASIC °³¹ßÇϸ鼭 ÇÕ¼ºÀ» Á÷Á¢ ÇÏ°Ô µÇ¾î »õ·Î¿î ±â¼úµµ ÀÍÈ÷°í ¾î´À Á¤µµ ÀÚ½ÅÀÖ°Ô µÇ¾ú½À´Ï´Ù. ¹«½¼ ±â¼úÀ̵ç Ã¥¸¸ º¸°í ÀÌÇØÇÑ´Ù°í µÇ´Â °ÍÀÌ ¾Æ´Ï°í ¿·¿¡¼­ º»´Ù°í µÇ´Â °Íµµ ¾Æ´Ï¸ç Á÷Á¢ óÀ½ºÎÅÍ ³¡±îÁö ÇؾßÁö Àڱ⠰ÍÀÌ µÇ´Â ¹ýÀ̴ϱî¿ä. )

°¡Àå ±âº»ÀûÀÎ »çÇ×


¸ÕÀú SYNOPSYÀÇ design compiler(dc_shell)¿¡¼­ ±âº»ÀûÀ¸·Î ¼³Á¤ÇØ¾ß ÇÒ º¯¼ö·Î ¾Æ·¡ÀÇ ³× °³°¡ ÀÖ½À´Ï´Ù.
dc_shell> search_path = search_path+{".","./lib",."/vhdl","./script"}
dc_shell> target_library = {target.db}
dc_shell> link_library = {link.db}
dc_shell> symbol_library = {symbol.sdb}
À§ÀÇ Àǹ̴ ¾Æ½Ã°ÚÁÒ? Search path´Â µÚ¿¡ ÁöÁ¤ÇÒ library ÆÄÀÏÀ» ãÀ» À§Ä¡¸¦ ÁöÁ¤ÇÏ´Â °ÍÀÌ°í(db directory¸¦ search_path¿¡ Æ÷ÇÔ½ÃÄÑ µÎ°í ±× °÷¿¡ ±âÁ¸¿¡ ÇÕ¼ºµÈ db°¡ ÀÖÀ¸¸é ÀÚµ¿À¸·Î linkµË´Ï´Ù.) target_library´Â ÇÕ¼ºÇÒ ¶§ »ç¿ëÇÒ technology library, link_library´Â ÀÌ¹Ì ÇÕ¼ºµÈ netlist°¡ ÀÖÀ» ¶§ ¾î¶² technology¸¦ »ç¿ëÇÏ¿© ¿¬°áÇÒ °ÍÀΰ¡¸¦ ÁöÁ¤ÇÕ´Ï´Ù. º¸Åë link_library´Â target_library¸¦ Æ÷ÇÔÇÏ°ÚÁö¿ä? Symbol_library´Â schematicÀ» º¸°íÀÚ ÇÒ ¶§ »ç¿ëÇÒ symbolÀÇ ¸ð¾çÀ» °¡Áö°í ÀÖ½À´Ï´Ù. ÀÌ·¸°Ô »ç¿ëÇÒ library fileµéÀ» ȯ°æ¿¡ ¿¬°á½ÃÄÑ ÁÖ¾î¾ß ÇÕ¼ºÀ» ½ÃÀÛÇÒ ¼ö ÀÖ½À´Ï´Ù. ±×¸®°í *´Â ÇöÀç dc_shell¿¡ ¿Ã¶ó¿Í ÀÖ´Â designµéÀ» ¶æÇÕ´Ï´Ù. (º¸Åë .synopsys_dc.setup ÆÄÀÏ¿¡ ¹Ì¸® ½á µÓ´Ï´Ù.)

DC(design compiler)¿¡¼­ cellÀ̳ª instance´Â Á¤¸»·Î instanceÀÇ À̸§ÀÔ´Ï´Ù. ÇØ´ç entity¿¡¼­ ºÒ·ÁÁö´Â hierarchy»óÀÇ À̸§ÀÌ°í¿ä, reference´Â instantiatedµÈ ±× entityÀÇ Á¾·ùÀÔ´Ï´Ù.
analyzeÇϸé default library ¶Ç´Â Á¤ÇØÁø Library ¿¡ µé¾î°¡´Â °ÍÀÌ°í(.mra, .syn, .sim ÆÄÀÏ »ý¼º)
elaborate´Â library¿¡ ÀÖ´Â ³»¿ëÀ» elaborateÇÏ´Â °ÍÀÔ´Ï´Ù.
±×¸®°í read = analyze + elaborate ¶ó°í »ý°¢ÇÏ½Ã¸é µË´Ï´Ù.
µû¶ó¼­
dc_shell> define_design_lib states -path ./lib
dc_shell> analyze -f vhdl my_pack.vhd -lib states
Çϸé my_pack.vhd°¡ analyzedµÇ¾î states¶ó´Â library(./lib¿¡ À§Ä¡)¿¡ µé¾î°©´Ï´Ù. default ·Î design_library´Â work°¡ µÇÁö¸¸ ¸¸¾à lib1À̶ó´Â library¿¡ analyzedµÇ¾î ÀÖ´Â leaf¶ó´Â entity¸¦ elaborateÇÏ°í ½ÍÀ¸¸é
dc_shell> elaborate leaf -library lib1
ÇÏ¸é µÇ´Â °ÍÀÔ´Ï´Ù.
¿¹)
dc_shell> read -format vhdl test.vhd
dc_shell> include constraints.scr
dc_shell> compile
dc_shell> write -f vhdl test -output test_netlist.vhd (netlist¸¦ vhdl·Î ¾¹´Ï´Ù.)

dc_shell> list search_path
dc_shell> find(cell,libA/LD1)
dc_shell> list -libraries

¶Ç, ÁÖÀÇÇÒ Á¡ÀÌ Àִµ¥ target_library¿¡´Â worst caseÀÇ library¸¸ ÁöÁ¤ÇØ ÁÖ°í, º°µµ·Î set_min_library ¸í·ÉÀ» »ç¿ëÇÏ¿© best case library¸¦ ÁöÁ¤ÇØ ÁØ ÈÄ¿¡ ÇÕ¼ºÇÒ ¶§´Â set_operating_conditions -max slow -min fast¿Í °°ÀÌ ÇѲ¨¹ø¿¡ ÁöÁ¤ÇØ ÁÖ°í max¿Í min¿¡ ´ëÇØ µ¿½Ã¿¡ constraint¸¦ ¸ÂÃßµµ·Ï ÇÕ¼ºÇÏ´Â °ÍÀÌ ¿äÁò(2004³â ±âÁØ)ÀÇ ¹æ¹ýÀÔ´Ï´Ù.

Constraints and Optimizing Designs


¸ÕÀú DC¿¡´Â µÎ °¡Áö constraints°¡ ÀÖ½À´Ï´Ù. Çϳª´Â design rule constraints ·Î max fanout, max transition, max capacitance°¡ Àִµ¥ ÀÌ°ÍÀº technology library ÀÚü°¡ ±ÔÁ¤ÇÏ´Â °ªÀ¸·Î¼­ ÀÌ°ÍÀ» À§¹ÝÇϸé ȸ·ÎÀÚü°¡ Á¦´ë·Î µ¿ÀÛÇÒ ¼ö ¾øÀ¸¹Ç·Î ¿ì¼±¼øÀ§°¡ ³ô½À´Ï´Ù(µû·Î ÁöÁ¤ÇÏÁö ¾ÊÀ¸¸é technolyg ÀÚü°¡ ±ÔÁ¤ÇÏ´Â Á¦ÇÑÀÌ Àû¿ëµË´Ï´Ù.). ´Ù¸¥ Çϳª´Â optimization constraints·Î¼­ speed¿Í area¸¦ optimizeÇÏ´Â °ÍÀÔ´Ï´Ù.

1. Design Rule Constraints
Set_max_fanout : ¾î¶² output ÀÌ driveÇÒ ¼ö ÀÖ´Â fanoutÀ» Á¦ÇÑÇÏ´Â °ÍÀ¸·Î ¸ðµç cell ¸¶´Ù fanout load°ªÀÌ ÀÖ½À´Ï´Ù. ÀÌ °ªµéÀº º¸Åë integer·Î Ç¥½ÃµÇ°í technology¿¡¼­ °áÁ¤ÇÏ´Â °ªÀÔ´Ï´Ù. ¾î¶² cellÀÇ fanout_load¸¦ ¾Ë°í ½ÍÀ¸¸é
dc_shell> get_attribute find(pin, "libA/AND2/i") fanout_load
¿Í °°ÀÌ ¾Ë¾Æ³¾ ¼ö ÀÖ½À´Ï´Ù.
set_max_transition : ¾î¶² netÀÇ RC(time constant)¿¡ ÀÇÇÑ rise ȤÀº fall timeÀ» Á¦ÇÑÇÒ ¶§ »ç¿ëÇÕ´Ï´Ù.
set_max_capacitance : transition time°ú µ¶¸³ÀûÀ¸·Î capacitance¸¦ Á¦ÇÑÇϴµ¥ »ç¿ëµÇ°í port³ª design¿¡ ´ëÇØ Àû¿ëÇÒ ¼ö ÀÖ½À´Ï´Ù.
¿¹¸¦ º¸¸é,
dc_shell> set_max_transition 5 test
dc_shell> set_max_fanout 5
dc_shell> set_max_capacitance 5

2. Optimization Constraints
DC´Â area¸¦ ÃÖÀûÈ­Çϱâ Àü¿¡ speed¸¦ ¸ÕÀú ÃÖÀûÈ­ÇÕ´Ï´Ù.
Synchronous ȸ·Î¿¡¼­´Â ±×·¸Áö¸¸
ÀüüÀÇ area´Â set_max_area·Î Àâ¾ÆÁÝ´Ï´Ù.(cell´ç area°¡ technology¿¡¼­ ÁÖ¾îÁöÁö¿ä?)
ÀϹÝÀûÀ¸·Î´Â
create_clock : Ŭ·°ÀÇ ÁÖÆļö¸¦ Á¤ÇØÁÖ°í
set_input_delay : ÀԷ½ÅÈ£°¡ clock¿¡ ºñÇØ ¾ó¸¶³ª ´Ê°Ô µé¾î¿À´ÂÁö¸¦ ¾Ë·Á ÁÖ±â À§ÇØ
set_output_delay : Ãâ·Â½ÅÈ£°¡ clockÀ» ±âÁØÀ¸·Î ¿ÜºÎ¿¡ ¾ó¸¶¸¸Å­ÀÇ Áö¿¬ÀÌ Ãß°¡·Î ÀÖÀ½À» ¾Ë·Á ÁÖ±â À§ÇØ(Àǹ̸¦ Á¤È®È÷ ¾Æ¼Å¾ß...Ŭ·°ÁֱⰡ 10nsÀÏ ¶§ output_delay¸¦ 3 ns·Î Çϸé ÇöÀç block¿¡¼­ clock edge±âÁØÀ¸·Î ÃÖ¼ÒÇÑ 7ns Àü¿¡ ½ÅÈ£°¡ ³ª°¡¾ß ÇÑ´Ù´Â ¶æÀÔ´Ï´Ù.)
set_driving_cell : ÀԷ½ÅÈ£¿¡ ´ëÇØ ¿ÜºÎ¿¡¼­ ¾î¶² cellÀÌ driveÇÏ°í ÀÖ´ÂÁö ¾Ë·ÁÁÜ(¾ó¸¶³ª ¼¼°Ô drivenµÇ´Â ½ÅÈ£ÀÎÁö, µû¶ó¼­ ±× ½ÅÈ£¸¦ ¹Þ¾Æ¼­ ¾µ ¶§ fan-outÀ» ¸ÂÃß±â À§ÇÑ bufferingÀ» ¾î´À Á¤µµ ÇØ Áà¾ß ÇÏ´ÂÁö ¾Ë·ÁÁÜ)
set_load : Ãâ·Â½ÅÈ£¿¡ ´ëÇØ ¿ÜºÎ¿¡ ¾ó¸¶¸¸Å­ÀÇ load°¡ ÀÖ´ÂÁö ¾Ë·ÁÁÜ(µû¶ó¼­ ¾ó¸¶³ª ¼¼°Ô driveÇØ Áà¾ß ÇÏ´ÂÁö ¾Ë·ÁÁÜ)
asynchronous path ½ÅÈ£¿¡ ´ëÇØ Áö¿¬°ªÀ» Á¤ÇØÁÖ±â À§Çؼ­´Â set_max_delay ¿Í set_min_delay ¸í·ÉÀ» »ç¿ëÇÕ´Ï´Ù. ÀÌ max_delay¿Í min_delay´Â ¶ÇÇÑ clockÀ» create_clock À» »ç¿ëÇÏ¿© °¡»óÀÇ Å¬·°À» ±âÁØÀ¸·Î Á¤ÇØÁÙ ¼öµµ ÀÖ½À´Ï´Ù. set_fix_hold¸í·ÉÀº delay¸¦ Ãß°¡ÇÔÀ¸·Î½á hold timeÀ§¹ÝÀ» Àâ¾ÆÁÝ´Ï´Ù.
max_area
optimization µµÁß¿¡´Â max_delay, min_delay, max_power, max_area¿¡ ´ëÇÑ cost°ªÀÌ ÃÖ¼Ò°¡ µÇµµ·Ï ȸ·Î°¡ ¿©·¯¹ø ¼öÁ¤µÇ´Â °ÍÀÔ´Ï´Ù.(cost°è»ê ¹æ½ÄÀº »ý·«)

3. timing report
ÇÕ¼ºÀ» ÇÒ ¶§¿¡´Â º¸Åë report_timing¸í·ÉÀ¸·Î timingÀ§¹ÝÀ» ¾Ë¾Æº½À¸·Î½á ÇÕ¼ºÀÌ ¼º°øÀûÀ¸·Î ÀÌ·ç¾îÁ³´ÂÁö ¾Ë ¼ö ÀÖ½À´Ï´Ù. report_timingÀº create_clockÀ¸·Î ¸¸µé¾îÁø clock path¿¡ ´ëÇؼ­ worst pathºÎÅÍ º¸¿©ÁÝ´Ï´Ù. ÀÔ·Â~·¹Áö½ºÅÍÀÇ ÀÔ·Â, ¶Ç´Â ·¹Áö½ºÅÍÀÇ Ãâ·ÂÀ¸·ÎºÎÅÍ ·¹Áö½ºÅÍÀÇ ÀÔ·Â, ÀԷ¿¡¼­ Ãâ·Â±îÁö, ·¹Áö½ºÅÍÀÇ Ãâ·Â¿¡¼­ Ãâ·Â±îÁö¿¡ ´ëÇؼ­ Á¤ÇØÁø timing¿ä±¸¿¡ ´ëÇØ °¡Àå ³ª»Û(¿ä±¸¸¦ ¸¸Á·½Ãų ¼öµµ ÀÖ°í ±×·¸Áö ¸øÇÒ ¼öµµ ÀÖ½À´Ï´Ù.) pathºÎÅÍ º¸¿©ÁÝ´Ï´Ù.
¿¹)
dc_shell> read -f verilog test.v
dc_shell> link_library = target_library = lsi_10k.db
dc_shell> create_clock clk -period 5
dc_shell> compile
dc_shell> report_timing -max_paths 5

4. ¸¹ÀÌ »ç¿ëµÇ´Â design compiler ¸í·Éµé
set_dont_touch : dont_touch´Â designÀ̳ª cell¿¡ ºÙ´Â attribute·Î¼­ ÀÏ´Ü setµÇ°í ³ª¸é ´õ ÀÌ»ó re-optimzedµÇÁö ¾Ê½À´Ï´Ù. dbÆÄÀÏ·Î saveÇÏ´õ¶óµµ ÀÌ ¼ºÁúÀº »ì¾ÆÀÖ½À´Ï´Ù. cell¿¡ set_dont_touchÇϸé ÇØ´ç designÀÇ cellÀÌ º¯ÇÏÁö ¾Ê´Â °ÍÀÌ°í design¿¡ set_dont_touchÇϸé ÇØ´ç referece´Â ¾îµð¿¡ instatiatedµÇ°Ç ¼öÁ¤µÇÁö ¾Ê½À´Ï´Ù. ¾Æ·¡¿Í °°ÀÌ »ç¿ëµË´Ï´Ù.
dc_shell> current_design = TOP
dc_shell> set_dont_touch u1 ¶Ç´Â set_dont_touch find(cell, u1)
¶Ç´Â
dc_shell> current_design = BlockB
dc_shell> set_dont_touch find(design,BlockA)
¶Ç report_referece³ª report_cell ¸í·ÉÀ¸·Î attribute¸¦ È®ÀÎÇÒ ¼ö ÀÖ°í remove_attribute·Î ¼ºÁúÀ» »èÁ¦ÇÒ ¼ö ÀÖ½À´Ï´Ù.

dc_shell> set_flatten true (hierarchy¸¦ flattenÇÏ´Â°Ô ¾Æ´Ô, combinational logicÀ» flattenÇÏ´Â °ÍÀÓ)
dc_shell> set_structure -timing true
dc_shell> report_compile_options
µµ ½áº¸Áø ¾Ê¾ÒÁö¸¸ ÇÊ¿äÇÒ °Í °°½À´Ï´Ù.

Sub-block A°¡ instance a1·Î ÀÖ°í ±× ¹Ø¿¡ u2°¡ ÀÖ´Ù¸é
dc_shell> ungroup a1 Çϸé a1/u2 ¶ó´Â »õ·Î¿î instance°¡ º¸ÀÌ°Ô µÇ°í
dc_shell> ungroup -flatten -all ÇÏ¸é ¸ðµÎ Ç®¾î¹ö¸³´Ï´Ù. (¹°·Ð dont_touchµÇ¾î ÀÖÀ¸¸é Á¦¿Ü)
¹Ý´ë·Î
dc_shell> group{u1 u2} -design_name new_block -cell_name Z1
µµ Àֳ׿ä.(Àǹ̴ ¾Æ½Ã°ÚÁÒ?)
dc_shell> set_dont_use libB/NAND2 (dont_use attribute¸¦ Ãß°¡, º¸Åë scan À» À§Çؼ­ scan typeÀ» Á¦¿ÜÇÏ°íÀÚ ÇÒ ¶§ »ç¿ëµË´Ï´Ù.)

5. characterize (Áß¿ä!)
¾î¶² design sub1°ú sub2°¡ °¢°¢ ¹«»çÈ÷ ÇÕ¼ºµÇ¾î top¿¡ »ç¿ëµÇ¾ú´Ù°í ÇսôÙ. ±×·±µ¥ top¿¡ µÎ°í º¸´Ï ÀÌÁ¦ constraint¸¦ À§¹ÝÇÏ°Ô µÉ ¼ö ÀÖ½À´Ï´Ù. (½ÇÁ¦·Î sub1°ú sub2¿¡ ÁÖ¾îÁø ȯ°æÀÌ °¢°¢À» ÇÕ¼ºÇÒ ¶§ ÁÖ¾ú´ø Á¶°Ç°ú ´Ù¸£±â ¶§¹®¿¡) ÀÌ·² °æ¿ì¿¡´Â sub1°ú sub2¸¦ characterizeÇÑ ÈÄ¿¡ ÀÌ Á¶°ÇÀ» write scriptÇÏ¿© ´Ù½Ã optimizeÇÒ ¼ö ÀÖ½À´Ï´Ù. ´ÙÀ½ÀÇ ¿¹¸¦ º¸¸é ¾Ë ¼ö ÀÖ½À´Ï´Ù.
(¿¹)
dc_shell> read -f db top.db
dc_shell> characterize u1 /* °¢°¢À» µû·Î characterizeÇÏ´Â °Ô ÁÁ°ÚÁÒ? */
dc_shell> current_design = sub1
dc_shell> write_script > sub1.scr
dc_shell> compile
dc_shell> current_design top
dc_shell> characterize u2
dc_shell> current_design = sub2
dc_shell> write_script > sub2.scr
dc_shell> compile
(¾Æ¸¶ script¸¦ writeÇÑ ÈÄ¿¡ compileÇϱâ Àü¿¡ ´Ù½Ã includeÇÏÁö ¾Ê¾Æµµ µÇ´Â °É·Î ¾Ë°í ÀÖ½À´Ï´Ù. write script´Â ³ªÁß¿¡ ½á¸Ô±â À§Çؼ­ ÇÕ´Ï´Ù.)

¿äÁòÀº toolÀÌ ÁÁ¾ÆÁ®¼­ º¸Åë 10¸¸ °ÔÀÌÆ®±îÁö´Â Çѹø¿¡ ÇÕ¼ºÇصµ ÁÁ´Ù°í ÇÕ´Ï´Ù.(½ÇÁ¦·Î ¿©·¯¹ø ±×·¸°Ô ÇØ ºÃ°í¿ä. Sub-blockºÎÅÍ ÇØ´çÇÏ´Â Áß°£ºí·°±îÁö ÇѲ¨¹ø¿¡ ÀÐ¾î µéÀÎ ÈÄ¿¡ constraint¸¦ ÁÖ°í ±×³É compileÇÕ´Ï´Ù.)

¼³°èµÈ ºí·°ÀÇ ¼º´É¿¡ ´ëÇØ ¾Æ¹« »ý°¢ÀÌ ¾øÀ» ¶§ ¾µ ¼ö ÀÖ´Â ¹æ¹ýÀ¸·Î..
¾Æ¹« Á¶°ÇÀ» ÁÖÁö¾Ê°í ÇÑ ¹ø compileÇÏ¿© timing_report¸¦ º» ÈÄ¿¡ Àû´çÇÑ Á¶°ÇÀ» ÁÖ°í ´Ù½Ã compileÇÑ ÈÄ¿¡
report_constraints -all_violators -verbose
¸¦ »ç¿ëÇÏ¿© À§¹ÝµÈ Á¶°ÇÀ» Á¶»çÇÑ ÈÄ¿¡ ´ÙÀ½°ú °°Àº °ÍÀ» ÇØ º¼ ¼ö ÀÖ½À´Ï´Ù.
- ´Ù¸¥ ±¸Á¶³ª ´Ù¸¥ ¹æ½ÄÀÇ ÄÚµù
- ½ÇÇö°¡´ÉÇÑ Á¶°ÇÀ¸·Î ¼öÁ¤
- false_path³ª multi-cycle path ÁöÁ¤
- asynch½ÅÈ£¿¡ ´ëÇØ max_delay/min_delay ÁöÁ¤
- group_path ÁöÁ¤ÇÏ¿© weight¸¦ ÁÖ´Â ¹ý(Cost °è»êÀÇ weight¸¦ Á¶Á¤ÇÏ¿© ƯÁ¤ path¿¡ ´ëÇØ ¹«½ÃÇѴٰųª À§¹ÝÀÌ ¸¹ÀÌ ³­ path¸¦ ÁýÁßÀûÀ¸·Î optimizeÇÏ°Ô ÇѴٰųª ÇÒ ¼ö ÀÖ°ÚÁÒ?)
- incremental compile¹æ¹ý(¾ÆÁÖ ¾à°£¸¸ ´õ ÇÏ¸é µÉ ¶§)

set_critical_range ´Â ¿¹¸¦ µé¾î worst¸¸ optimizeÇÏ´Â °Ô ¾Æ´Ï¶ó worst¿¡¼­ 2.0 ns¾ÈÀ¸·Î violatedµÈ net±îÁö °°ÀÌ optimizeÇÏ°í ½ÍÀ» ¶§ ¾µ ¼ö ÀÖ´Ù°í ÇÕ´Ï´Ù.(½áº¸Áø ¾Ê¾Ò½À´Ï´Ù¸¸..)
¶Ç´Â compileÇÑ ÈÄ constraint¸¦ ¾à°£ ´õ ½ÉÇÏ°Ô ÁÖ°í ´Ù½Ã compileÇصµ µË´Ï´Ù.

Hierarchical designÀÇ °æ¿ì
dc_shell> current_design = top
dc_shell> characterize u1
dc_shell> current_design = s1
dc_shell> compile
dc_shell> current_design = top
dc_shell> characterize u2
dc_shell> current_design = s2
dc_shell> compile
¿Í °°Àº ¹æ¹ýÀÌ °¡Àå ¸¹ÀÌ »ç¿ëµÇ´Â ¹æ¹ýÀ̶ó°í ÇÕ´Ï´Ù. (½ÇÁ¦·Î Á¦°¡ ´ã´çÇÑ ASIC °³¹ßÀÇ °æ¿ìµµ ÀÌ·± compile-characterize-compile ¹æ½Äµµ ¾²¿´°í bottom-up ¹æ½Ä, Áï compile-set_dont_touch-read ¹æ½Äµµ ¾²¿´¾ú½À´Ï´Ù. °æ¿ì¿¡ µû¶ó ´Ù¸¥ °Í °°½À´Ï´Ù.)

ÇÕ¼ºÀ» ÇÑ ÈÄ CTS(Clock Tree Synthesis) À» Æ÷ÇÔÇÑ P&RÀ» Çϱâ Àü¿¡´Â pre-simulationÀ» Çϱâ À§Çؼ­´Â clock driver³ª global reset driver¿¡ set_ideal_networkÀ̶ó°í ÇØ ÁÖ¾î¾ß SDF¸¦ »ÌÀ» ¶§ driving strength¸¦ ¹«½ÃÇÏ°í »ç¿ëÇÒ ¼ö ÀÖ´Â SDF°¡ ³ª¿É´Ï´Ù.